ATMEGA169P-16MCU【PDF 82/274 页】MCU AVR 16K ISP FLSH 16MHZ 64QFN

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PIC16F946

DS41265A-page 170

Preliminary

2005 Microchip Technology Inc.

14.3

Enabling SPI I/O

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

SDI is automatically controlled by the SPI module

SDO must have TRISC<4> bit cleared

SCK (Master mode) must have TRISC<6> bit

cleared

SCK (Slave mode) must have TRISC<6> bit set

SS must have TRISA<5> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

14.4

Typical Connection

Figure 14-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be

programmed to the same Clock Polarity (CKP), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

Master sends data – Slave sends dummy data

Master sends data – Slave sends data

Master sends dummy data – Slave sends data

FIGURE 14-2:

SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSPM<3:0> = 010xb

Serial Clock

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